These features enable engineering teams to more rapidly create new designs or upgrade existing designs to Virtex-6 FPGAs. ![]() Synphony HLS also generates fixed-point C-models that can be used for system validation and functional verification. The Synphony HLS product generates optimized RTL for Virtex-6 FPGA implementation as well as testbench scripts to verify that the RTL implementation behaves exactly as the original model. The high level synthesis flow provides Virtex-6 FPGA users with more automatic target-specific optimizations and architecture exploration from high level models and delivers up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing today announced that its Synphony HLS ( High Level Synthesis) product now includes optimized support for Xilinx Virtex®-6 FPGAs. MOUNTAIN VIEW, Calif., June 3 / PRNewswire-FirstCall/ - Synopsys, Inc.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |